This invention relates to the fabrication of field effect transistors, and in particular to a method which permits control of the threshold potential of such devices.
As field effect transistors and integrated circuits in which they are used have increased in complexity and precision, the need for precisely tailoring the voltage at which the transistors turn on (i.e., threshold voltage) has become increasingly important. At the same time, the reduction in size of these devices has introduced parasitics which put severe constraints on impurity doping in the semiconductor. For example, a typical method employed to adjust threshold is to form a surface implant in the entire device area after formation of the field oxide regions and prior to formation of the source and drain regions. The gate electrodes are then defined by depositing a layer of polycrystalline silicon (polysilicon) everywhere, forming photoresist patterns over the desired gate regions and then etching the exposed polysilicon regions. This is followed by formation of the source and drain regions aligned with the gate electrodes. Such an approach is usually adequate. However, as channel lengths decrease, it is desirable to increase substrate doping to avoid so-called short channel effects which adversely affect the I-V characteristics of the transistors. If high concentration channel doping is included throughout the device area, the junction capacitances will increase thereby decreasing device speed.
Ion implantation limited to the channel regions for adjustment of threshold has been previously suggested. (See, for example, U.S. Pat. No. 4,212,100 issued to Paivinen et al, and U.S. Pat. No. 4,217,149 issued to Sawazaki.) Such techniques, which suggest use of an SiO.sub.2 mask to define the implanted region, generally require separate mask alignments to form the implant and to define the gate electrodes and/or the source and drain regions.
It is therefore a primary object of the invention to provide a technique for precisely tailoring the threshold of a field effect transistor by introduction of impurities limited to the region at and below the channel of the transistor. It is a further object of the invention to provide a means for self-alignment of the impurity region with gate electrode and source and drain regions.